XMSRC4392-VC1¶

1. Introduction¶

1.1 Product Description¶

XMSRC4392 is a high-performance four-channel asynchronous audio sample rate converter based on XMOS high-performance chips, specifically designed for professional audio applications. Compared to the SRC4392's dual-channel SRC solution, this product provides double the processing capability while achieving significant optimization in both cost and performance.

• The product integrates two independent SRC modules (SRC_A and SRC_B), each capable of processing two audio channels, supporting ultra-high sampling rates up to 768KHz, providing exceptional flexibility and high-performance audio sample rate conversion for various digital audio systems.
• Supports SSRC sample rate conversion between 44.1KHz-768KHz, ASRC sample rate conversion between 44.1KHz-192KHz, and processes 16bit/24bit/32bit audio data.
• The product features excellent audio performance specifications, with both SSRC and ASRC THD+N (@1kHz, 0dBFs) ≤ -130dB, providing audio equipment manufacturers with professional-grade audio processing solutions.

1.2 Product Features¶

1.3 Application Scenarios¶

1.4 Product Block Diagram¶

1.5 Ordering Information¶

2. Modes and Specifications¶

2.1 Supported Input/Output Modes¶

XMSRC4392-VC1 employs a flexible input/output routing architecture, supporting multiple audio processing modes. The following lists typical application modes from a data flow perspective:

2.2 Detailed Parameters for Each Operating Mode¶

2.2.1 Mode 1: Single S/PDIF to I²S Output¶

Application Scenario: Converting two S/PDIF signals to I²S output, suitable for digital audio systems

Data Flow:

Signal Flow Diagram:

                ┌→ SRC_A ──→ I²S_A_DATA_OUT (Master)
S/PDIF_IN (4-to-1) ┤
                └→ SRC_B ──→ I²S_B_DATA_OUT (Master)

Parameter Description:

2.2.2 Mode 2: Single I²S Input Dual Output (Pass-Through + Conversion)¶

Application Scenario: I²S_A input signal simultaneously passes through to output and is output from I²S_B after SRC conversion, suitable for scenarios where one source signal requires two different output sample rates

Data Flow:

Signal Flow Diagram:

                    ┌→ I²S_A_DATA_OUT (Slave, pass-through)
I²S_A_DATA_IN (Slave) ┤
                    └→ SRC_A ──→ I²S_B_DATA_OUT (Master)

Parameter Description:

2.2.3 Mode 3: Dual I²S Input Cross Conversion Output¶

Application Scenario: Two I²S inputs are cross-output after SRC conversion, suitable for scenarios where dual audio channels need simultaneous conversion with swapped output interfaces

Data Flow:

Signal Flow Diagram:

I²S_A_DATA_IN ──→ SRC_A ──┐
                          ├→ I²S_B_DATA_OUT
I²S_B_DATA_IN ──→ SRC_B ──┤
                          └→ I²S_A_DATA_OUT

Parameter Description:

2.2.4 Mode 4: S/PDIF and I²S Bidirectional Conversion¶

Application Scenario: S/PDIF input converts to I²S output while I²S input converts to S/PDIF output, suitable for digital audio format bidirectional conversion applications

Data Flow:

Signal Flow Diagram:

S/PDIF_IN (4-to-1) ──→ SRC_A ──→ I²S_A_DATA_OUT (Master)

I²S_B_DATA_IN (Slave) ──→ SRC_B ──→ S/PDIF_OUT

Parameter Description:

2.2.5 Mode 5: I²S to S/PDIF Output + Other I²S Pass-Through¶

Application Scenario: I²S_A input converts to S/PDIF output, I²S_B independently passes through, suitable for applications where one channel requires format conversion and the other passes directly

Data Flow:

Signal Flow Diagram:

I²S_A_DATA_IN (Slave) ──→ SRC_A ──→ S/PDIF_OUT

I²S_B_DATA_IN (Master) ──→ I²S_B_DATA_OUT (Master, pass-through)

Parameter Description:

2.3 Audio Performance Specifications¶

2.4 Feature Comparison¶

3. Pin Configuration and Functions¶

3.1 XMSRC4392_VC1 Pin Layout¶

3.2 XMSRC4392_VC1 Pin Description¶

4. Configuration Interface Description¶

4.1 I²C/UART Configuration Interface¶

XMSRC4392-VC1 supports both I²C and UART dual-protocol configuration, providing flexible configuration methods. The configuration interface type can be selected via pin 22 (X0D31) UART_I2C_SEL signal: | Configuration Method | Pin 22 (X0D31) | Communication Interface | Description | |:--------|:-------------|:---------|:-----| | Pull-up | UART_I2C_SEL | UART mode | Pin 9 (X0D29) = UART_RX, Pin 23 (X0D32) = UART_TX | | Pull-down | UART_I2C_SEL | I²C mode | Pin 9 (X0D29) = I2C_SDA, Pin 21 (X0D30) = I2C_SCL |

4.2 Configurable Parameters¶

The following parameters can be configured via I²C or UART interface:

4.3 MCLK Output Frequency Configuration¶

MCLK_OUT frequency is determined by the clock domain and configured multiplier (128fs/256fs/512fs/1024fs).

5. Hardware Parameters¶

5.1 Normal Operating Conditions¶

5.2 Product Dimensions¶

13±0.1mm(L)X13±0.1mm(W)X0.8±0.1mm(H)

5.3 Module Package Diagram¶

6. Minimum System Reference Design¶

7. Product Packaging Information¶

Tray + Outer Box Packaging

8. Revision History¶

9. Inquiry and Feedback¶